An Overview of Multi-Core Network-on-Chip System to Enable Task Parallelization Using Intelligent Adaptive Arbitration
Küçük Resim Yok
Tarih
2021
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Springer Science and Business Media Deutschland GmbH
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
Increasing the count of transistors packed within integrated circuits necessitates efficient communication architecture such as Network-on-Chip (NoCs) to deal with scalability, bandwidth, latency, and optimized CPU core utilization goals. To extend the applicability of Moore’s law, multiprocessor architectures have been introduced, which in turn requires a higher level of synchronization and concurrency to enable enhancement in system performance. This research deals with global communication for NoC-multi-core system using the Intelligent Adaptive Arbitration technique to enable task parallelization by showing a perspective for the deployment of Intelligent Adaptive Arbitration on different NoC architecture(s) to enable parallel computing with fair bandwidth distribution and low latency. This research also opens up room for the various network-on-chip topology to constitute a unification of the latest trends of intra-chip communication. © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
Açıklama
3rd Symposium on Intelligent Manufacturing and Mechatronics, SympoSIMM 2020 -- 10 August 2020 through 10 August 2020 -- Perlis -- 261469
Anahtar Kelimeler
Arbitration, Fair bandwidth, Intelligent adaptive arbitration, Multi-core, Network-on-Chip (NoC), Synchronization, System-on-Chip (SoC)
Kaynak
Lecture Notes in Mechanical Engineering
WoS Q Değeri
Scopus Q Değeri
Q4
