Tuna, M.Fidan, C.B.Koyuncu, I.Pehlivan, I.2024-09-292024-09-292016978-150901679-2https://doi.org/10.1109/SIU.2016.7495988https://hdl.handle.net/20.500.14619/926824th Signal Processing and Communication Application Conference, SIU 2016 -- 16 May 2016 through 19 May 2016 -- Zonguldak -- 122605In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the Route & Place processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard. © 2016 IEEE.trinfo:eu-repo/semantics/closedAccessChaosChaotic systemFPGAVHDLConference Object10.1109/SIU.2016.74959882-s2.0-849828338171312N/A1309