Alptekin, SebahaddinTan, Serhat OrkunAltindal, Semsettin2024-09-292024-09-2920191536-125X1941-0085https://doi.org/10.1109/TNANO.2019.2952081https://hdl.handle.net/20.500.14619/6178The capacity/conductivity-voltage (C/G-V) data of the PVP interlayered metal-semiconductor structure were examined at +/- 4V biases and 1-500 kHz frequency interval at room temperature. The surface states (N-ss) in the insulation layer and the metal-semiconductor interface are seen as the main causes of high capacitance and conductivity values at low frequencies. AC signals, which result in an increase in capacitance and conductivity values, are easily monitored by N-ss at low frequencies. The graph extracted against the conductivity and frequency logarithm (G(p)/omega-log(f)) indicates a peak appearance as a result of the N-ss effect. In the energy range of (E-c -0.423) - (E-c-0.604), surface states (N-ss) and relaxation times (tau) values alter from 8.71 x 10(11) to 5.84 x 10(11) eV(-1) cm(-2) and 6.54x10(-6) s to 1.10x10(-4) s, respectively.eninfo:eu-repo/semantics/closedAccessPolymersmetal-semiconductor structureelectric admittancesurface statesrelaxation timesArticle10.1109/TNANO.2019.29520812-s2.0-850756592791199Q2119618WOS:000547508700001Q2