Yazar "Tuna, Murat" seçeneğine göre listele

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    Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator
    (Springer, 2020) Koyuncu, Ismail; Tuna, Murat; Pehlivan, Ihsan; Fidan, Can Bulent; Alcin, Murat
    In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated by uniting the chaotic system-based RNG and the RO-based RNG structures on FPGA. The chaotic oscillator structure as the basic entropy source has been implemented in VHDL using Euler numerical algorithm in 32-bit IQ-Math fixed point number standart on FPGA. The designed chaotic oscillator has been synthesized for the FPGA chip and the statistics related to chip resource consumption and clock frequencies of the units have been presented. The RO-based RNG structure has been designed as the second entropy source. Chaos-ring based dual entropy core novel TRNG unit have been created by combining of these two FPGA-based structures in the XOR function used at the post processing unit. The throughput of the designed dual entropy core TRNG unit ranges 464 Mbps. The output bit streams obtained from FPGA-based novel TRNG have been subjected to NIST 800-22 test suites.
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    Effective and Reliable Speed Control of Permanent Magnet DC (PMDC) Motor under Variable Loads
    (Springer Singapore Pte Ltd, 2015) Tuna, Murat; Fidan, Can Bulent; Kocabey, Sureyya; Gorgulu, Sertac
    This paper presents the effective and reliable speed control of PMDC motors under variable loads and reference speeds. As is known DC motors are more preferred in industrial practices. This is that, the PMDC motors don't require brush and commutator care and to increase in torque per motor depending on developments in power electronics. In this study, proportional-integral controller (PI) and fuzzy logic controller (FL) have been designed for speed control of PMDC motor. In the design of these controllers, characteristics such as minimum overrun time, response time to the load, settling time and ideal rise time have been taken into consideration for better stability performance. In this design, the best system response was searched by examining the effect of different defuzzification methods onto the fuzzy logic system response. In conclusion, it has been seen that FL controller has a better performance for variable speed-load control of PMDC motor compared to PI controller.
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    Electronic circuit design, implementation and FPGA-based realization of a new 3D chaotic system with single equilibrium point
    (Elsevier Gmbh, 2016) Tuna, Murat; Fidan, Can Bulent
    In this study, numerical, analog and digital circuit modellings were presented with 3 dimensional, continuous, autonomous new chaotic system. Lyapunov exponentials spectrum and bifurcation diagram were presented with timing series of the new chaotic system, phase portraits and Lyapunov exponentials, equilibrium points, dissipativity analyses. Then, analog-based electronic circuit of the new chaotic system is designed in OrCAD-Pspice. It has been observed that it is a very good match on phase portrait results obtained with the numerical analyses, analog circuit simulation Finally, the new chaotic system presented has been numerically realized in two different models by using Heun and RK4 algorithms with discrete time on FPGA, in order to develop embedded chaos-based engineering applications. In creating Heun and RK4-based two different models of the new chaotic system on FPGA, 32 byte IEEE 754-1985 floating point numerical format was used and coded in VHDL format. Designed chaotic systems were synthesized and tested with Xilinx ISE design tool. Chip statistics obtained from the Place&Route operation in Xilinx Virtex-6 family xc6v1x75t-3ff784 FPGA chip of the Heun and RK4-based designed chaotic system were presented. Max operation frequency of the new FPGA-based chaotic signal generator modelled by using two different numerical algorithms is determined as 390.067 MHz. Newly presented chotic system's computer-based numerical simulation was used to realize error analyses fort he design implemented on FPGA. According to the absolute error analysis results, the covergence of 34.456E-5 precision was obtained bwtween the PC-based numerical model and the FPGA-based new chaotic system model. (C) 2016 Elsevier GmbH. All rights reserved.
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    High speed FPGA-based chaotic oscillator design
    (Elsevier Science Bv, 2019) Tuna, Murat; Alcin, Murat; Koyuncu, Ismail; Fidan, Can Bulent; Pehlivan, Ihsan
    In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with fixed-point number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex-6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random number generation. (C) 2019 Elsevier B.V. All rights reserved.
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    Kaos tabanlı çift entropi çekirdekli gerçek rasgele sayı üreteci tasarımı ve FPGA üzerinde gerçekleştirilmesi
    (Karabük Üniversitesi, 2017) Tuna, Murat; Fidan, Can Bülent
    Bu tez çalışmasında, FPGA üzerinde 4 farklı nümerik algoritma kullanılarak tasarımı gerçekleştirilen 2 adet yeni kaotik sistem ile 1 adet ring osilatör yapıları kullanılarak, yüksek çalışma ve bit üretim hızına sahip kaos tabanlı çift entropi çekirdekli Gerçek Rasgele Sayı Üreteçleri (GRSÜ) gerçekleştirilmiştir. Bu çalışma doğrultusunda, ilk olarak son yıllarda literatüre sunulan ve üzerinde FPGA ile çalışma yapılmamış farklı matematiksel özelliklere sahip 8 adet kaotik sistem seçilmiştir. Bu sistemlerin matematiksel denklem yapıları incelenerek bilgisayar ortamında nümerik çözümleri elde edilmiştir. Ayrıca kaotik sistemlerin zaman serileri, faz portreleri ve Lyapunov üstelleri gibi kaotik dinamik analizleri gerçekleştirilmiştir. İkinci aşamada; referans olarak seçilen Pehlivan C Kaotik Sistemi (PCKS) ve Pehlivan 3 Boyutlu Kaotik Sistemi (P3BKS) dört farklı nümerik metot ile modellenmiş ve sistemlerin dinamik davranışları incelenerek kaos analizleri yapılmıştır. Yine bu aşamada PCKS ve P3BKS tasarımları FPGA üzerinde donanım tanımlama dili VHDL ile 32 bit IQ-Math sabit noktalı sayı standardına uygun olarak modellenmiştir. Modelleme aşamasında Euler, Heun, RK4 ve RK5-Butcher olmak üzere dört farklı algoritma kullanılmıştır. Xilinx Virtex–6 ailesi XC6VLX75T-3FF784 nolu çipi kullanılan tasarımlar Xilinx ISE Design Tools 14.2 benzetim programı kullanılarak sentezlenmiştir. Ayrıca bu aşamada FPGA üzerinde VHDL dili kullanılarak ring osilatör tasarımı gerçekleştirilmiştir. Kaotik ve ring osilatör tasarımlarının FPGA çip kaynak kullanımına ve ünitelerin saat hızlarına ait parametrelerinin istatistikleri incelenmiştir. Elde edilen sonuçlara göre ring osilatörün çalışma frekansı 1,5 GHz, kaotik osilatörlerin çalışma frekansı 390-464 MHz dolaylarında değişmektedir. Bu aşamada tasarımlardan elde edilen sonuçlar literatürdeki benzer çalışmalarla karşılaştırılmıştır. Üçüncü aşamada; Euler, Heun, RK4 ve RK5-Butcher algoritmaları kullanılarak FPGA-tabanlı PCKS ve P3BKS tasarımları ile ring osilatör yapısı birleştirilerek çift entropi çekirdekli yeni GRSÜ tasarımı gerçekleştirilmiştir. Genel olarak iki farklı kaotik sistem, dört farklı nümerik algoritma ve bir kuantalama işlemi ile toplamda 8 farklı GRSÜ ünitesi tasarlanmıştır. FPGA tabanlı GRSÜ modellemelerinde 32 bit IQ-Math sabit noktalı sayı standardı kullanılmıştır. Geliştirilen modeller VHDL donanım tanımlama dili kullanılarak kodlanmıştır. Tasarımı yapılan 8 farklı GRSÜ ünitesi Xilinx firmasının ürettiği Virtex-6 ailesinin XC6VLX75T-3FF784 çipi için sentezlenerek, FPGA çip kaynak kullanımına ve ünitelerin saat hızlarına ait parametrelerin istatistikleri incelenmiştir. GRSÜ ünitelerinin verileri işleme süreleri Xilinx ISE Design Tools 14.2 simülasyon programı kullanılarak elde edilmiştir. Tasarlanan yeni GRSÜ üniteleri sistemin belirtilen çalışma frekansında yaklaşık olarak 390-464 Mbit/s arasında değişen yüksek bit üretim hızları elde edilmiştir. Son aşamada; FPGA üzerinde kaos tabanlı çift entropi çekirdekli tasarlanan 8 adet GRSÜ'lerinden elde edilen sayı dizilerinin rasgelelik testleri gerçekleştirilmiştir. Test aşamasında literatürde yoğun bir şekilde kullanılan uluslararası FIPS 140-1 ve NIST 800-22 test paketleri kullanılmıştır. Tasarımı gerçekleştirilen 8 adet GRSÜ ünitesinden alınan 20 Kbit sayı dizileri FIPS testlerine, 1 Mbit sayı dizileri NIST testlerine tabi tutulmuştur. Tüm tasarımlar rasgelelik testlerinden son işlem uygulamasına gerek kalmadan geçerek, sistemin çalışma frekansı ile aynı değerlerde yüksek bit üretim hızları (390-464 Mbit/s) elde edilmiş ve buda önerilen yeni tasarımın özgün bir çalışma olduğunu göstermiştir. Kaotik osilatörlerin gürültü benzeri özellikler taşımaları ve bilgi işaretini gizleyebilme gibi özelliklerinden dolayı kaos tabanlı GRSÜ yapıların geliştirilmesi üzerine son yıllarda büyük çabalar sarf edilmektedir. Rasgele sayı üreteçleri kriptografi, Monte-Carlo metodunun kullanıldığı uygulamalar, bilgisayar benzetimleri ve modellemeleri ile sayısal analiz uygulamaları gibi birçok alanda kullanılmaktadır. Bu tez çalışmasında FPGA üzerinde kaos tabanlı çift entropi çekirdekli tasarımı gerçekleştirilen yeni GRSÜ ünitelerinden elde edilen yüksek çalışma ve bit üretim hızına sahip rasgele sayı dizileri; hızlı, güvenli ve yoğun işlem gerektiren kriptografi ve güvenli haberleşme alanlarında kullanılabileceklerdir.
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    Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
    (Ieee, 2016) Tuna, Murat; Fidan, Can Bulent; Koyuncu, Ismail; Pehlivan, Ihsan
    In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the Route&Place processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.
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    Real Time Implementation of A Novel Chaotic Generator on FPGA
    (Ieee, 2015) Tuna, Murat; Koyuncu, Ismail; Fidan, Can Bulent; Pehlivan, Ihsan
    In this study, a new continuous-time autonomous chaotic system has been presented and implemented on FPGA. Presented a new chaotic system has been designed using the IEEE 754-1985 floating-point format and implemented using Heun algorithm with VHDL language. The designed system has been synthesized and tested on Xilinx Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based a new chaotic signal generator is certain as 390 MHz and performance results have been given with chip statistics. In addition, the results obtained from FPGA-based new chaotic generator have been compared with the Matlab-based numerical results and it has been observed that obtained results are successful. By the developed FPGA-based novel chaotic system model, chaos-based various engineering applications such as true random number generation and secure communication system can be performed.
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    A Study on the importance of chaotic oscillators based on FPGA for true random number generating (TRNG) and chaotic systems
    (Gazi Univ, Fac Engineering Architecture, 2018) Tuna, Murat; Fidan, Can Bulent
    The random number generators are used in many areas such as cryptography, the applications where the Monte-Carlo method is used, the application of numerical analysis with computer simulations and modeling. TRNGs that is used in the field of cryptography and secure communications require fast, secure and intensive process of the physical methods that do not have deterministic character are used as entropy source. These methods are direct reinforcement, dual oscillator and chaos-based applications. In recent years the great efforts are being made in the area of developing the chaos-based TRNG structures due to noise-like features and the ability of hiding informatory sign of chaotic oscillators. Chaos based TRNG's within the digital circuits are an effective alternative to the traditional chaos-based analog structure. Because TRNG systems that use analog chaotic signal generator are difficult to be synchronized with the transmitter and receiver. In addition, the weak resources that generates physical noises like thermal or scattering are used on the implementation of these circuits. The digital-based FPGA chips have a significant potential in improving the information security capabilities in some applications as cryptology and securing the communication which requires high performance and processor power. In this study, performance differences between conventional method of TRNG that used chaotic system and recently designed FPGA based chaotic systems have been compered.