Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
Küçük Resim Yok
Tarih
2016
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Ieee
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the Route&Place processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.
Açıklama
24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEY
Anahtar Kelimeler
Chaos, Chaotic system, FPGA, VHDL
Kaynak
2016 24th Signal Processing and Communication Application Conference (Siu)
WoS Q Değeri
N/A
