Real time hardware implementation of the 3D chaotic oscillator which having golden-section equilibra

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dc.contributor.authorTuna, M.
dc.contributor.authorFidan, C.B.
dc.contributor.authorKoyuncu, I.
dc.contributor.authorPehlivan, I.
dc.date.accessioned2024-09-29T16:16:43Z
dc.date.available2024-09-29T16:16:43Z
dc.date.issued2016
dc.departmentKarabük Üniversitesien_US
dc.description24th Signal Processing and Communication Application Conference, SIU 2016 -- 16 May 2016 through 19 May 2016 -- Zonguldak -- 122605en_US
dc.description.abstractIn this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the Route & Place processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard. © 2016 IEEE.en_US
dc.identifier.doi10.1109/SIU.2016.7495988
dc.identifier.endpage1312en_US
dc.identifier.isbn978-150901679-2
dc.identifier.scopus2-s2.0-84982833817en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.startpage1309en_US
dc.identifier.urihttps://doi.org/10.1109/SIU.2016.7495988
dc.identifier.urihttps://hdl.handle.net/20.500.14619/9268
dc.indekslendigikaynakScopusen_US
dc.language.isotren_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.ispartof2016 24th Signal Processing and Communication Application Conference, SIU 2016 - Proceedingsen_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectChaosen_US
dc.subjectChaotic systemen_US
dc.subjectFPGAen_US
dc.subjectVHDLen_US
dc.titleReal time hardware implementation of the 3D chaotic oscillator which having golden-section equilibraen_US
dc.title.alternativeAltin Oran Denge Noktalarina Sahip 3 Boyutlu Bir Kaotik Osilatörün Gerçek Zamanli Donanimsal Gerçeklemesien_US
dc.typeConference Objecten_US

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