Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra

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dc.authoridFIDAN, CAN BULENT/0000-0001-5252-6301
dc.authoridPehlivan, Ihsan/0000-0001-6107-655X
dc.contributor.authorTuna, Murat
dc.contributor.authorFidan, Can Bulent
dc.contributor.authorKoyuncu, Ismail
dc.contributor.authorPehlivan, Ihsan
dc.date.accessioned2024-09-29T16:11:27Z
dc.date.available2024-09-29T16:11:27Z
dc.date.issued2016
dc.departmentKarabük Üniversitesien_US
dc.description24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEYen_US
dc.description.abstractIn this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the Route&Place processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.en_US
dc.description.sponsorshipIEEE,Bulent Ecevit Univ, Dept Elect & Elect Engn,Bulent Ecevit Univ, Dept Biomed Engn,Bulent Ecevit Univ, Dept Comp Engnen_US
dc.identifier.endpage1312en_US
dc.identifier.isbn978-1-5090-1679-2
dc.identifier.startpage1309en_US
dc.identifier.urihttps://hdl.handle.net/20.500.14619/8436
dc.identifier.wosWOS:000391250900304en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.language.isotren_US
dc.publisherIeeeen_US
dc.relation.ispartof2016 24th Signal Processing and Communication Application Conference (Siu)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectChaosen_US
dc.subjectChaotic systemen_US
dc.subjectFPGAen_US
dc.subjectVHDLen_US
dc.titleReal Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibraen_US
dc.typeConference Objecten_US

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